Adder circuits within a data processor commonly have three inputs: a first addend A-input (A.sub.in), a second addend B-input (B.sub.in), and a Carry-input (C.sub.in), to produce an output having both a Sum-out (S.sub.out) and a Carry-out (C.sub.out). A plurality of three-input adder circuits are commonly grouped together to form an arithmetic logic unit (ALU). The ALU is utilized within a data processing unit to execute a variety of data processing instructions, such as a multiply instruction.
Some arithmetic processing applications require a summation of a large number of binary numbers. A known circuit having multiple inputs to accommodate such applications is a multilevel carry-save adder. In one form, four data inputs exist and a four-input adder circuit is used. However, a conventional four-input adder circuit requires two full adder circuits (four half-adder circuits), and a significant increase in die area to be implemented. Therefore, known four-input adder circuits are not commonly implemented in general purpose data processors.